In current systems, parallel cyclic redundancy check (CRC) computations involve decomposing an N-bit message into small blocks. Each block has a fixed size (M). The fixed size typically equals the polynomial degree. Most approaches include computing the CRC of a message and performing a series of N/M Galois multiply-accumulate operations. Each of the N/M blocks is multiplied by a pre-stored coefficient, divided by the CRC polynomial, and added to the accumulator. Accordingly, these systems require N/M Galois parallel multiply-accumulate operations.
There are a number of disadvantages to such approaches. For example, Galois multipliers typically require the use of special hardware with a considerable number of logical gates. Conventional Galois multiplier architectures consume large areas of silicon. Moreover, Galois operations are rarely used in common applications. Furthermore, the CRC ploynomial is typically hardwired into an efficient Galois multiplier. Such a design is not reconfigurable to support other polynomials.
There is therefore a need for a system and method that includes modulo-2 multiplications for repetitive operations in CRC computations that optimize processing efficiency and maximize capacity.